A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology

TLDR

The paper introduces a 90‑nm CMOS 10‑Gb/s transceiver designed for chip‑to‑chip communications. The transceiver employs a 5‑tap decision‑feedback equalizer in the receiver and a 4‑tap baud‑spaced feed‑forward equalizer in the transmitter, powered by a PLL‑based LC VCO and using half‑rate architectures with a speculative‑feedback half‑rate DFE to meet loop‑timing requirements at 10 Gb/s. The design delivers error‑free NRZ signaling over channels with losses exceeding 30 dB, produces a 1200 mVppd output while consuming only 300 mW per transmitter/receiver pair, and experimental tests confirm the effectiveness of the FFE/DFE equalization.

Abstract

This paper presents a 90-nm CMOS 10-Gb/s transceiver for chip-to-chip communications. To mitigate the effects of channel loss and other impairments, a 5-tap decision feedback equalizer (DFE) is included in the receiver and a 4-tap baud-spaced feed-forward equalizer (FFE) in the transmitter. This combination of DFE and FFE permits error-free NRZ signaling over channels with losses exceeding 30 dB. Low jitter clocks for the transmitter and receiver are supplied by a PLL with LC VCO. Operation at 10-Gb/s with good power efficiency is achieved by using half-rate architectures in both transmitter and receiver. With the transmitter producing an output signal of 1200mVppd, one transmitter/receiver pair and one PLL consume 300mW. Design enhancements of a half-rate DFE employing one tap of speculative feedback and four taps of dynamic feedback allow its loop timing requirements to be met. Serial link experiments with a variety of test channels demonstrate the effectiveness of the FFE/DFE equalization