J. Barth

A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC

H.L. Kalter, C.H. Stapper, J. Barth et al. · IEEE Journal of Solid-State Circuits · 1990 · 114 citations

Engineering, Computer Engineering, Electrical Engineering +16

Processor-based built-in self-test for embedded DRAM

J. Dreibelbis, J. Barth, H.L. Kalter et al. · IEEE Journal of Solid-State Circuits · 1998 · 84 citations

Engineering, Computer Engineering, Electrical Engineering +17

Embedded DRAM: Technology platform for the Blue Gene/L chip

Subramanian S. Iyer, J. Barth, P. Parries et al. · IBM Journal of Research and Development · 2005 · 75 citations

Engineering, Computer Engineering, Electrical Engineering +16

A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier

J. Barth, W. Reohr, P. Parries et al. · IEEE Journal of Solid-State Circuits · 2008 · 60 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache

J. Barth, Kavita Nair, Nianzheng Cao et al. · IEEE Journal of Solid-State Circuits · 2010 · 52 citations

Engineering, Computer Engineering, Electrical Engineering +17