P. Parries

22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL

P. Chang, C. Ortolland, David Fried et al. · 2012 · 89 citations

High-performance Soi Technology, Engineering, Vlsi Design +16

Embedded DRAM: Technology platform for the Blue Gene/L chip

Subramanian S. Iyer, J. Barth, P. Parries et al. · IBM Journal of Research and Development · 2005 · 75 citations

Hardware Security, Non-volatile Memory, Electrical Engineering +15

A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier

J. Barth, W. Reohr, P. Parries et al. · IEEE Journal of Solid-State Circuits · 2008 · 59 citations

Hardware Security, Non-volatile Memory, Electrical Engineering +15

An 800-MHz embedded DRAM with a concurrent refresh mode

T. Kirihata, P. Parries, David R. Hanson et al. · IEEE Journal of Solid-State Circuits · 2005 · 50 citations

Hardware Security, Non-volatile Memory, Engineering +12

Scaling deep trench based eDRAM on SOI to 32nm and Beyond

G. Wang, D. Anand, Nauman Zafar Butt et al. · 2009 · 45 citations

Electrical Engineering, Engineering, Vlsi Design +9