T. Kirihata

Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips

Norm Robson, John Safran, C. Kothandaraman et al. · 2007 · 80 citations

Hardware Security, Electrical Engineering, Manycore Processor +14

A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier

J. Barth, W. Reohr, P. Parries et al. · IEEE Journal of Solid-State Circuits · 2008 · 59 citations

Hardware Security, Non-volatile Memory, Electrical Engineering +15

A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache

J. Barth, Kavita Nair, Nianzheng Cao et al. · IEEE Journal of Solid-State Circuits · 2010 · 52 citations

Low-power Electronics, Non-volatile Memory, Electrical Engineering +14

Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM

Sami Rosenblatt, Daniel Fainstein, Alberto Cestero et al. · IEEE Journal of Solid-State Circuits · 2013 · 50 citations

Hardware Security, Electrical Engineering, Engineering +12

An 800-MHz embedded DRAM with a concurrent refresh mode

T. Kirihata, P. Parries, David R. Hanson et al. · IEEE Journal of Solid-State Circuits · 2005 · 50 citations

Hardware Security, Non-volatile Memory, Engineering +12