Memories of tomorrow

W. Reohr, H. Honigschmid, R. P. Robertazzi, +13

IEEE Circuits and Devices Magazine

Non-volatile MemoryEngineeringEmerging Memory TechnologyComputer ArchitectureShort Read +15

Asynchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz

S.E. Schuster, W. Reohr, Peter W. Cook, +3

Hardware SecurityEngineeringVlsi DesignClock RecoverySynchronization Protocol +13

A 10 ns read and write non-volatile memory array using a magnetic tunnel junction and FET switch in each cell

R.E. Scheuerlein, W. J. Gallagher, S. Parkin, +4

Non-volatile MemoryEngineeringComputer ArchitectureNon-volatile StorageHardware Security +15

Rethinking Refresh: Increasing Availability and Reducing Power in DRAM for Cache Applications

Philip Emma, W. Reohr, Mesut Meterelliyoz

IEEE Micro

Storage (Memory)Memory ArchitectureEngineeringCache ApplicationsData Science +11

A High-Speed 128-kb MRAM Core for Future Universal Memory Applications

J. DeBrosse, D. Gogl, Ann-Christin Bette, +12

IEEE Journal of Solid-State Circuits

Hardware SecurityNon-volatile MemoryElectrical EngineeringEngineeringComputer Engineering +12

A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier

J. Barth, W. Reohr, P. Parries, +14

IEEE Journal of Solid-State Circuits

Hardware SecurityNon-volatile MemoryElectrical EngineeringSoi TechnologyEngineering +13

A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache

J. Barth, Kavita Nair, Nianzheng Cao, +8

IEEE Journal of Solid-State Circuits

Low-power ElectronicsNon-volatile MemoryElectrical EngineeringNs Random AccessEngineering +12

A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier

J. Barth, W. Reohr, P. Parries, +14

Electrical EngineeringEngineeringVlsi DesignDram MacroRandom Cycle 1.5Ns-latency +9

A high-speed 128 Kbit MRAM core for future universal memory applications

Ann-Christin Bette, J. DeBrosse, D. Gogl, +12

Non-volatile MemoryEngineeringComputer ArchitectureComplementary Reference CellsMulti-channel Memory Architecture +14

A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache

J. Barth, Don Plass, Erik Nelson, +7

On-chip L3 CacheNon-volatile MemoryElectrical EngineeringEngineeringVlsi Design +10