IEEE Journal of Solid-State Circuits · 2005 · 50 citations · 17 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureMemoryMicroelectronicsClock ManagementEmbedded Memory BlocksMemory HierarchyMemory Hierarchy DesignMemory Subsystem DesignRegister-transfer Level DesignControl RegistersDynamic Random-access Memory DesignMemory UtilizationRedundancy AllocationRedundancy LogicRegistersResource Redundancy AllocationScheduler Design
An 800-MHz embedded DRAM macro employs a memory cell utilizing a device from the 90-nm high-performance technology menu; a 2.2-nm gate oxide 1.5 V IO device. A concurrent refresh mode is designed to improve the memory utilization to over 99% for a 64 /spl mu/s data retention time. A concurrent refresh scheduler utilizes up-count and down-count registers to identify at least one array to be refreshed at every clock cycle, emulating a classical distributed refresh mode. A command multiplier employs low frequency phased clock signals to generate the clock, commands, and addresses at rates up to 4/spl times/ that of the tester frequency. The macro integrates masked redundancy allocation logic during at speed multibank test. The hardware results show a 312-MHz random access frequency and 800-MHz multibank frequency at 1.2 V, respectively.
17
Processor-based built-in self-test for embedded DRAM
J. Dreibelbis, J. Barth, H.L. Kalter et al. · IEEE Journal of Solid-State Circuits · 1998 · 84 citations
Engineering, Computer Engineering, Electrical Engineering +17
A multimedia 32 b RISC microprocessor with 16 Mb DRAM
Toshihisa Shimizu, J. Korematu, M. Satou et al. · 2002 · 57 citations