D. Anand

Scaling deep trench based eDRAM on SOI to 32nm and Beyond

G. Wang, D. Anand, Nauman Zafar Butt et al. · 2009 · 45 citations

Engineering, Computer Engineering, Electrical Engineering +17

Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering

J. Barth, J. Dreibelbis, Erik Nelson et al. · IBM Journal of Research and Development · 2002 · 25 citations

Engineering, Computer Engineering, Electrical Engineering +16

A 300MHz multi-banked, eDRAM macro featuring GND sense, bit-line twisting and direct reference cell write

J. Barth, D. Anand, J. Dreibelbis et al. · 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) · 2005 · 24 citations

Engineering, Computer Engineering, Electrical Engineering +11

A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining

J. Barth, D. Anand, Steven M. Burns et al. · IEEE Journal of Solid-State Circuits · 2005 · 24 citations

Engineering, Computer Engineering, Electrical Engineering +15

An on-chip self-repair calculation and fusing methodology

D. Anand, B. Cowan, O. Farnsworth et al. · IEEE Design & Test of Computers · 2003 · 23 citations

Engineering, Computer Engineering, Computer Systems +15