G. Wang

High performance 14nm SOI FinFET CMOS technology with 0.0174µm<sup>2</sup> embedded DRAM and 15 levels of Cu metallization

C-H. Lin, B. Greene, J. Cai et al. · 2014 · 128 citations

22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL

P. Chang, C. Ortolland, David Fried et al. · 2012 · 89 citations

High-performance Soi Technology, Engineering, Vlsi Design +16

Scaling deep trench based eDRAM on SOI to 32nm and Beyond

G. Wang, D. Anand, Nauman Zafar Butt et al. · 2009 · 45 citations

Electrical Engineering, Engineering, Vlsi Design +9

Analysis of Retention Time Distribution of Embedded DRAM - A New Method to Characterize Across-Chip Threshold Voltage Variation

Weiran Kong, P. Parries, G. Wang et al. · 2008 · 32 citations

Non-volatile Memory, Engineering, Memory Design +17

45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications

Subramanian S. Iyer, G. Freeman, Colin J. Brodsky et al. · IBM Journal of Research and Development · 2011 · 18 citations

Engineering, Vlsi Design, Emerging Memory Technology +16