Fluctuation limits & amp; scaling opportunities for CMOS SRAM cells

Abstract

Fundamental limitations on scaling CMOS SRAM cell transistor dimensions and operating voltages are demonstrated by measuring the local stochastic distributions of read, write and retention DC margins of 65nm PDSOI CMOS SRAM cells. DC measurements show, for the first time, the write operation to be more fluctuation limited. Measurements also reveal fundamental insights into terminal voltage dependencies of the fluctuations of cell storage node voltages - observations that are engaged to increase cell immunity to fluctuations by several orders of magnitude by biasing the cell terminal voltages appropriately