R. Divakaruni

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

N. Loubet, Terence B. Hook, P. Montanini et al. · 2017 · 939 citations

Engineering, Nanocomputing, Semiconductor Device +17

Challenges and future directions for the scaling of dynamic random-access memory (DRAM)

J. Mandelman, R.H. Dennard, G. Bronner et al. · IBM Journal of Research and Development · 2002 · 262 citations

Non-volatile Memory, Engineering, Dynamic Random-access Memory +16

Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

Haining Yang, R. Malik, Y. Li et al. · 2005 · 142 citations

Electrical Engineering, Physical Design (Electronics), Engineering +13

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

Ruijie Xie, P. Montanini, Kerem Akarvardar et al. · 2016 · 139 citations

Engineering, Electron-beam Lithography, Finfet Technology +18

High performance 14nm SOI FinFET CMOS technology with 0.0174µm<sup>2</sup> embedded DRAM and 15 levels of Cu metallization

C-H. Lin, B. Greene, J. Cai et al. · 2014 · 128 citations