Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

N. Loubet, Terence B. Hook, P. Montanini, +61

EngineeringNanocomputingSemiconductor DeviceAdvanced Packaging (Semiconductors)Nanoelectronics +15

Power and Technology Scaling into the 5 nm Node with Stacked Nanosheets

Terence B. Hook

Joule

Materials ScienceElectrical EngineeringNanoscale SystemEngineeringNanosheet +10

Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond

Seong-Dong Kim, Michael Guillorn, Isaac Lauer, +3

EngineeringVlsi DesignComputer ArchitectureNanocomputingAc Performance Evaluation +18

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

Ruijie Xie, P. Montanini, Kerem Akarvardar, +84

EngineeringElectron-beam LithographyFinfet TechnologyMechanical EngineeringWafer Scale Processing +16

Lateral ion implant straggle and mask proximity effect

Terence B. Hook, J. Brown, P.E. Cottrell, +4

IEEE Transactions on Electron Devices

Device ModelingMask Proximity EffectElectrical EngineeringIon ImplantationEngineering +12

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

Kwangyou Seo, Bala Haran, Divya Gupta, +81

EngineeringVlsi DesignFinfet TechnologyIntegrated CircuitsWafer Scale Processing +16

Switching-Speed Limitations of Ferroelectric Negative-Capacitance FETs

Zhi Cheng Yuan, Shahriar Rizwan, Michael Wong, +7

IEEE Transactions on Electron Devices

EngineeringSwitching-speed LimitationsMagnetic MaterialsMultiferroicsFerroelectric Application +15

High performance and low power transistors integrated in 65nm bulk CMOS technology

Zuying Luo, An Steegen, M. Eller, +38

Low-power ElectronicsLow Power ApplicationsElectrical EngineeringEngineeringVlsi Design +10

The effects of fluorine on parametrics and reliability in a 0.18-μm 3.5/6.8 nm dual gate oxide CMOS technology

Terence B. Hook, E.L. Adler, F Guarin, +3

IEEE Transactions on Electron Devices

Electrical EngineeringNm Dual GateEngineeringGate PolysiliconInterface Trap Density +11

High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering

V. Chan, R. Rengarajan, N. Rovedo, +16

High Speed 45NmElectrical EngineeringGate LengthEngineeringAdvanced Packaging (Semiconductors) +13