R. Malik

Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

Haining Yang, R. Malik, Y. Li et al. · 2005 · 142 citations

Electrical Engineering, Physical Design (Electronics), Engineering +13

22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL

P. Chang, C. Ortolland, David Fried et al. · 2012 · 89 citations

High-performance Soi Technology, Engineering, Vlsi Design +16

Strain for CMOS performance improvement

V. Chan, K. Rim, Meikei Leong et al. · 2006 · 54 citations

Engineering, Vlsi Design, Mechanical Engineering +18

Scaling deep trench based eDRAM on SOI to 32nm and Beyond

G. Wang, D. Anand, Nauman Zafar Butt et al. · 2009 · 45 citations

Electrical Engineering, Engineering, Vlsi Design +9

Nanotechnology: Regulatory Outlook on Nanomaterials and Nanomedicines in United States, Europe and India

R. Malik, Sharvil Patil · Applied Clinical Research Clinical Trials and Regulatory Affairs · 2019 · 23 citations · Full text

Nanoparticles, Nano Medicines, Nanotherapeutics +27