S. Jain

High performance 14nm SOI FinFET CMOS technology with 0.0174µm<sup>2</sup> embedded DRAM and 15 levels of Cu metallization

C-H. Lin, B. Greene, J. Cai et al. · 2014 · 128 citations

Ti and NiPt/Ti liner silicide contacts for advanced technologies

Praneet Adusumilli, Emre Alptekin, M. Raymond et al. · 2016 · 31 citations

Materials Engineering, Materials Science, Electrical Engineering +15

High performance bulk planar 20nm CMOS technology for low power mobile applications

Huiling Shang, S. Jain, E. Josse et al. · 2012 · 26 citations

Low-power Electronics, High Density, Electrical Engineering +14

45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications

Subramanian S. Iyer, G. Freeman, Colin J. Brodsky et al. · IBM Journal of Research and Development · 2011 · 18 citations

Engineering, Vlsi Design, Emerging Memory Technology +16

A highly rugged 19 dBm 28GHz PA using novel PAFET device in 45RFSOI technology achieving peak efficiency above 48%

Shafiullah Syed, S. Jain, Dimitri Lederer et al. · 2020 · 15 citations

Electrical Engineering, Engineering, Rf Semiconductor +12