Hun-Jan Tao

An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling

C.H. Diaz, Hun-Jan Tao, Yao-Ching Ku et al. · IEEE Electron Device Letters · 2001 · 148 citations

Engineering, Electrical Engineering, Microelectronics +16

A 25-nm gate-length FinFET transistor module for 32nm node

Chang-Yun Chang, Tsung-Lin Lee, C. Wann et al. · 2009 · 62 citations

Engineering, Computer Engineering, Electrical Engineering +17

A spectroscopic analysis of phase separation behavior of polyurethane in restricted geometry: chain rigidity effects

Hun-Jan Tao, Curtis W. Meuse, Xiaozhen Yang et al. · Macromolecules · 1994 · 36 citations · Full text

Natural Sciences, Chemistry, Materials Science +17

A low operating power FinFET transistor module featuring scaled gate stack and strain engineering for 32/28nm SoC technology

Chih-Chieh Yeh, Chih-Sheng Chang, Hong-Nien Lin et al. · 2010 · 33 citations

Engineering, Computer Engineering, Electrical Engineering +17

Application of a Molecular Simulation Technique for Prediction of Phase-Separated Structures of Semirigid Model Polyurethanes

Hun-Jan Tao, William J. MacKnight, Shaw Ling Hsu et al. · Macromolecules · 1994 · 30 citations

Natural Sciences, Chemistry, Materials Science +17