Hong-Nien Lin

In<inf>0.53</inf>Ga<inf>0.47</inf>As MOSFETs with high channel mobility and gate stack quality fabricated on 300 mm Si substrate

M. L. Huang, S. W. Chang, M. K. Chen et al. · 2015 · 32 citations

Semiconductors, Semiconductor Technology, Electrical Engineering +12

A low operating power FinFET transistor module featuring scaled gate stack and strain engineering for 32/28nm SoC technology

Chih-Chieh Yeh, Chih-Sheng Chang, Hong-Nien Lin et al. · 2010 · 32 citations

Low-power Electronics, Electrical Engineering, Engineering +13

High-performance p-channel Schottky-barrier SOI FinFET featuring self-aligned PtSi source/drain and electrical junctions

Horng‐Chih Lin, Mengfan Wang, Fu-Ju Hou et al. · IEEE Electron Device Letters · 2003 · 28 citations

Electrical Engineering, Self-aligned Ptsi Source/drain, Engineering +11

Correlating drain-current with strain-induced mobility in nanoscale strained CMOSFETs

Hong-Nien Lin, Hung-Wei Chen, Chih-Hsin Ko et al. · IEEE Electron Device Letters · 2006 · 24 citations

Electrical Engineering, Engineering, Nanoelectronics +10

A 32nm CMOS Low Power SoC Platform Technology for Foundry Applications with Functional High Density SRAM

Shien-Yang Wu, Chung-Cheng Chou, C.Y. Lin et al. · 2007 · 19 citations

Low-power Electronics, System On Chip, Electrical Engineering +13