Per‐Erik Hellström

Author

Per‐Erik Hellström

Also Known As

Hellstrom, P.E., Hellstrom, Per-Erik, Hellström, Per-Erik, P E Hellström, P. E. Hellstrom, P. E. Hellström, P.-E Hellstrom, P.-E Hellström, P.-E. Hellstrom, P.-E. Hellström

146

Publications

1.2K

Citations

H-Index

Concepts

All Affiliations

KTH Royal Institute of Technology Uppsala University University of Warwick University of Stuttgart Newcastle University

About

Per‐Erik Hellström is an author at KTH Royal Institute of Technology specializing in engineering, applied physics, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	18	36	735
2	Applied Physics	17	34	696
3	Chemical Engineering	2	2	25
4	Natural Sciences	1	1	13
5	Biomedical Engineering	1	1	20

Per‐Erik Hellström

Publications

790

Citations

H-Index

Page 1

	Year	Citations
Lateral encroachment of Ni-silicides in the source/drain regions on ultrathin silicon-on-insulator J. Seger, Per‐Erik Hellström, Jun Lü, Applied Physics Letters EngineeringLateral EncroachmentSilicon On InsulatorChannel RegionSemiconductor Device	2005	43
Sidewall transfer lithography for reliable fabrication of nanowires and deca-nanometer MOSFETs Julius Hållstedt, Per‐Erik Hellström, Henry H. Radamson Thin Solid Films Electrical EngineeringDeca-nanometer MosfetsEngineeringBeam LithographyMicrofabrication	2008	39
550 °C 4H-SiC p-i-n Photodiode Array With Two-Layer Metallization S. Hou, Per‐Erik Hellström, Carl‐Mikael Zetterling, IEEE Electron Device Letters Semiconductor TechnologyRoom TemperatureElectrical EngineeringElectronic DevicesEngineering	2016	36
A robust spacer gate process for deca-nanometer high-frequency MOSFETs Julius Hållstedt, Per‐Erik Hellström, Z. Zhang, Microelectronic Engineering Electrical EngineeringEngineeringHigh-frequency DeviceNanoelectronicsElectronic Engineering	2005	34
Reduced self-heating by strained silicon substrate engineering A.G. O’Neill, R. Agaiby, Sarah H. Olsen, Applied Surface Science EngineeringMicrofabricationBias Temperature InstabilityApplied PhysicsSemiconductor Device Fabrication	2008	33
A novel strained Si/sub 0.7/Ge/sub 0.3/ surface-channel pMOSFET with an ALD TiN/Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O<sub>3</sub> gate stack Depei Wu, A.-C. Lindgren, Stefan Persson, IEEE Electron Device Letters Semiconductor TechnologyAld Tin/al/sub 2/O/subElectrical EngineeringSi ReferenceEngineering	2003	30
Characterization of transfer-bonded silicon bolometer arrays Frank Niklaus, J. Pejnefors, Matteo Dainese, Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE	2004	29
Performance Fluctuation of FinFETs With Schottky Barrier Source/Drain Zhen Zhang, Jun Lü, Zhi‐Jun Qiu, IEEE Electron Device Letters Semiconductor TechnologyElectrical EngineeringEngineeringNanoelectronicsElectronic Engineering	2008	28
Hole effective mass in silicon inversion layers with different substrate orientations and channel directions Luca Donetti, F. Gámiz, S. Thomas, Journal of Applied Physics EngineeringHole Effective MassHole TransportSilicon On InsulatorSemiconductor Device	2011	26
Effects of Carbon on Schottky Barrier Heights of NiSi Modified by Dopant Segregation Jun Luo, Zhi‐Jun Qiu, D.W. Zhang, IEEE Electron Device Letters Materials EngineeringMaterials ScienceSemiconductorsBoron DiffusionEngineering	2009	26

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