S. Balakrishnan

A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm/sub 2/ SRAM cell

C. Auth, S. Balakrishnan, M. Bost et al. · 2005 · 230 citations

Engineering, Computer Engineering, Electrical Engineering +17

The Impact of Performance Asymmetry in Emerging Multicore Architectures

S. Balakrishnan, Ravi Rajwar, Mike Upton et al. · 2005 · 154 citations

Computing, Computer Science, Computer Systems +12

Optimal Price and Quantity Determination for Retail Electric Power Contracts

Steven A. Gabriel, Antonio J. Conejo, M.A. Plazas et al. · IEEE Transactions on Power Systems · 2006 · 138 citations

Business, Supply Chain Management, Contract Theory +16

A simulation approach to balancing annual risk and reward in retail electrical power markets

Steven A. Gabriel, Murat Genç, S. Balakrishnan · IEEE Transactions on Power Systems · 2002 · 64 citations

Management, Risk Management, Supply Chain Management +16

Copper Die Bumps (First Level Interconnect) and Low-K Dielectrics in 65nm High Volume Manufacturing

A. Yeoh, Ming Chang, C. Pelto et al. · 2006 · 61 citations

Engineering, Computer Engineering, Electrical Engineering +17