C. Pelto

A 14nm logic technology featuring 2<sup>nd</sup>-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm<sup>2</sup> SRAM cell size

S. Natarajan, M. Agostinelli, Sheikh A. Akbar et al. · 2014 · 521 citations

-Generation Finfet, Rectangular Fins, Engineering +16

A 10nm high performance and low-power CMOS technology featuring 3^rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects

C. Auth, A. Aliyarukunju, M. Asoro et al. · 2017 · 353 citations

Engineering, Integrated Circuits, High Performance +18

A 32nm logic technology featuring 2<sup>nd</sup>-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm<sup>2</sup> SRAM cell size in a 291Mb array

S. Natarajan, M Armstrong, M. Bost et al. · 2008 · 184 citations

Engineering, Vlsi Design, Channel Strain +17

Low-k interconnect stack with multi-layer air gap and tri-metal-insulator-metal capacitors for 14nm high volume manufacturing

K. Fischer, M. Agostinelli, C. Allen et al. · 2015 · 67 citations

Engineering, Vlsi Design, Logic Product +19

Enabling Next Generation 3D Heterogeneous Integration Architectures on Intel Process

Adel Elsherbini, K. Jun, Shawna M. Liff et al. · 2022 International Electron Devices Meeting (IEDM) · 2022 · 63 citations

Heterogeneous Computing, Engineering, Device Integration +23