M. Agostinelli

A 14nm logic technology featuring 2<sup>nd</sup>-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm<sup>2</sup> SRAM cell size

S. Natarajan, M. Agostinelli, Sheikh A. Akbar et al. · 2014 · 532 citations

Engineering, Computer Engineering, Electrical Engineering +16

Tunable replica circuits and adaptive voltage-frequency techniques for dynamic voltage, temperature, and aging variation tolerance

James Tschanz, Keith Bowman, Steve Walstra et al. · 2009 · 137 citations

Engineering, Computer Engineering, Electrical Engineering +17

BTI reliability of 45 nm high-K + metal-gate process technology

Sangwoo Pae, M. Agostinelli, M. Brazier et al. · 2008 · 131 citations

Engineering, Electrical Engineering, Materials Science +17

Erratic fluctuations of sram cache vmin at the 90nm process technology node

M. Agostinelli, J. Hicks, Jianzhong Xu et al. · 2006 · 117 citations

Engineering, Computer Engineering, Electrical Engineering +17

RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications

C.-H. Jan, M. Agostinelli, H. Deshpande et al. · 2010 · 84 citations

Engineering, Electrical Engineering, Microelectronics +16