A 90-nm logic technology featuring strained-silicon

Scott E. Thompson, M Armstrong, C. Auth, +25

IEEE Transactions on Electron Devices

Electrical EngineeringEngineeringNanoelectronicsStress-induced Leakage CurrentApplied Physics +8

A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications

C.-H. Jan, Uma Bhattacharya, R. Brain, +20

EngineeringVlsi DesignComputer ArchitecturePower ElectronicsHardware Security +16

RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications

C.-H. Jan, M. Agostinelli, H. Deshpande, +19

EngineeringVlsi DesignRf SocIntegrated CircuitsHigh-speed Electronics +14

A 32nm SoC platform technology with 2<sup>nd</sup> generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications

C.-H. Jan, M. Agostinelli, Markus J. Buehler, +41

EngineeringVlsi DesignComputer ArchitectureIntegrated CircuitsHigh Performance +18

A 65nm CMOS SOC Technology Featuring Strained Silicon Transistors for RF Applications

I. Post, M.S. Akbar, G. Curello, +13

Low-power ElectronicsPmos TransistorsElectrical EngineeringRf ApplicationsEngineering +9

A 14 nm SoC platform technology featuring 2<sup>nd</sup> generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um<sup>2</sup> SRAM cells, optimized for low power, high performance and high density SoC products

C.-H. Jan, F. Al-Amoody, H.-Y. Chang, +31

Edge 14EngineeringVlsi DesignNm Gate PitchComputer Architecture +15

A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors

C.-H. Jan, Peng Bai, S. Biswas, +35

Robust ReliabilityEngineeringVlsi DesignIntegrated CircuitsPower Electronics +15

A 65nm ultra low power logic platform technology using uni-axial strained silicon transistors

C.-H. Jan, Peng Bai, Jaeseok Choi, +29

Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignEdge 65Nm +7

A 32nm low power RF CMOS SOC technology featuring high-k/metal gate

P. Vandervoorn, M. Agostinelli, S.-J. Choi, +31

Low-power ElectronicsElectrical EngineeringEngineeringHigh-k/metal GateRf Semiconductor +11

A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications

Yuxiao Wang, Jiefeng Lin, Yat Hon Ng, +13

EngineeringVlsi DesignEmerging Memory TechnologyComputer ArchitectureIntegrated Circuits +18