A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

C. Auth, C. Allen, A. Blattner, +44

Low-power Cmos TechnologyEngineeringVlsi DesignTri-gate TransistorsIntegrated Circuits +17

A 10nm high performance and low-power CMOS technology featuring 3^rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects

C. Auth, A. Aliyarukunju, M. Asoro, +53

EngineeringIntegrated CircuitsHigh PerformanceInterconnect (Integrated Circuits)High-speed Electronics +16

A high performance 180 nm generation logic technology

Shih‐Chi Yang, Sally Ahmed, B. Arcot, +22

Low-power ElectronicsMaterials EngineeringElectrical EngineeringEngineeringVlsi Design +11

Self-heat reliability considerations on Intel's 22nm Tri-Gate technology

C. Prasad, Lei Jiang, D. Singh, +19

EngineeringSelf-heat Reliability ConsiderationsComputer ArchitectureExcellent MatchingThermal Modeling +14

A 32nm SoC platform technology with 2<sup>nd</sup> generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications

C.-H. Jan, M. Agostinelli, Markus J. Buehler, +41

EngineeringVlsi DesignComputer ArchitectureIntegrated CircuitsHigh Performance +18

A comparison of state-of-the-art NMOS and SiGe HBT devices for analog/mixed-signal/RF circuit applications

Kelin J. Kuhn, R. Basco, D. Becher, +5

Electrical EngineeringEngineeringAnalog/mixed-signal/rf Circuit ApplicationsRf SemiconductorHigh-frequency Device +12

A 65nm CMOS SOC Technology Featuring Strained Silicon Transistors for RF Applications

I. Post, M.S. Akbar, G. Curello, +13

Low-power ElectronicsPmos TransistorsElectrical EngineeringRf ApplicationsEngineering +9

Source/drain extension scaling for 0.1 μm and below channel length MOSFETs

Scott E. Thompson, P. Packan, T. Ghani, +7

Electrical EngineeringEngineeringVlsi DesignSource/drain ExtensionTechnology Scaling +8

Investigation of boron diffusion in polysilicon and its application to the design of p-n-p polysilicon emitter bipolar transistors with shallow emitter junctions

I. Post, P. Ashburn

IEEE Transactions on Electron Devices

EngineeringBoron Polysilicon EmittersSilicon On InsulatorSemiconductor DeviceSemiconductors +15

A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors

C.-H. Jan, Peng Bai, S. Biswas, +35

Robust ReliabilityEngineeringVlsi DesignIntegrated CircuitsPower Electronics +15