A high performance 180 nm generation logic technology

Abstract

A 180 nm generation logic technology has been developed with high performance 140 nm L/sub GATE/ transistors, six layers of aluminum interconnects and low-/spl epsi/ SiOF dielectrics. The transistors are optimized for a reduced 1.3-1.5 V operation to provide high performance and low power. The interconnects feature high aspect ratio metal lines for low resistance and fluorine doped SiO/sub 2/ inter-level dielectrics for reduced capacitance. 16 Mbit SRAMs with a 5.59 /spl mu/m/sup 2/ 6-T cell size have been built on this technology as a yield and reliability test vehicle.