Reza Arghavani

30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays

R. Chau, J. Kavalieros, B. Roberds et al. · 2002 · 110 citations

Electrical Engineering, Engineering, Vlsi Design +11

A 50 nm depleted-substrate CMOS transistor (DST)

R. Chau, J. Kavalieros, Barry M. Doyle et al. · 2002 · 101 citations

Electrical Engineering, Engineering, Nanoelectronics +11

A high performance 180 nm generation logic technology

Shih‐Chi Yang, Sally Ahmed, B. Arcot et al. · 2002 · 89 citations

Low-power Electronics, Materials Engineering, Electrical Engineering +13

Advanced Depleted-Substrate Transistors: Single-gate, Double-gate and Tri-gate

R. Chau, B.S. Doyle, J. Kavalieros et al. · 2002 · 75 citations

Electrical Engineering, Engineering, Advanced Depleted-substrate Transistors +3

An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7 - 1.4 V

Scott E. Thompson, Morteza S. Alavi, Reza Arghavani et al. · 2002 · 62 citations

Low-power Electronics, Low Power, Electrical Engineering +15