Reza Arghavani - Concepedia

Author

Reza Arghavani

Also Known As

Arghavani, Reza, Christopher Nordquist, Lisa Tracy, Normand Modine, R. Arghavani, Reza Arghavani, Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States), Vijay Narayanan

Publications

846

Citations

H-Index

Concepts

All Affiliations

Intel (United States)Lam Research (United States)Applied Materials (United States)Pennsylvania State University University of Florida

About

Reza Arghavani is an author at Intel (United States) specializing in engineering, electrical engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	15	18	788
2	Applied Physics	13	16	675
3	Computer Engineering	8	8	368
4	Medicine	1	1	17
5	Computer Science	1	1	12

Reza Arghavani

Publications

788

Citations

H-Index

Page 1

	Year	Citations
30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays R. Chau, J. Kavalieros, B. Roberds, Electrical EngineeringEngineeringVlsi DesignNanoelectronicsBias Temperature Instability	2002	110
A 50 nm depleted-substrate CMOS transistor (DST) R. Chau, J. Kavalieros, Barry M. Doyle, Electrical EngineeringEngineeringNanoelectronicsBias Temperature InstabilityMixed-signal Integrated Circuit	2002	101
A high performance 180 nm generation logic technology Shih‐Chi Yang, Sally Ahmed, B. Arcot, Low-power ElectronicsMaterials EngineeringElectrical EngineeringEngineeringVlsi Design	2002	89
Advanced Depleted-Substrate Transistors: Single-gate, Double-gate and Tri-gate R. Chau, B.S. Doyle, J. Kavalieros, Electrical EngineeringEngineeringAdvanced Depleted-substrate TransistorsApplied PhysicsSemiconductor Device Fabrication	2002	75
An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7 - 1.4 V Scott E. Thompson, Morteza S. Alavi, Reza Arghavani, Low-power ElectronicsLow PowerElectrical EngineeringNm TechnologyEngineering	2002	62
High-frequency response of 100 nm integrated CMOS transistors with high-K gate dielectrics Douglas W. Barlage, Reza Arghavani, G. Dewey, Pmos TransistorsElectrical EngineeringEngineeringHigh-frequency DeviceNanoelectronics	2002	46
Stress Management in Sub-90-nm Transistor Architecture Reza Arghavani, Zhaohe Yuan, Nilesh P. Ingle, IEEE Transactions on Electron Devices Materials ScienceMaterials EngineeringElectrical EngineeringEngineeringDielectric Films	2004	41
Impact of Transistor Architecture (Bulk Planar, Trigate on Bulk, Ultrathin-Body Planar SOI) and Material (Silicon or III–V Semiconductor) on Variation for Logic and SRAM Applications Nidhi Agrawal, Yoshie Kimura, Reza Arghavani, IEEE Transactions on Electron Devices EngineeringVlsi DesignIntegrated CircuitsTransistor PerformanceSilicon On Insulator	2013	40
Manufacturable Processes for $\leq$ 32-nm-node CMOS Enhancement by Synchronous Optimization of Strain-Engineered Channel and External Parasitic Resistances Atif Noori, Mihaela Balseanu, Pieter Boelen, IEEE Transactions on Electron Devices EngineeringVlsi DesignIntegrated CircuitsInterconnect (Integrated Circuits)Semiconductor Device	2008	39
A reliable and manufacturable method to induce a stress of >1 GPa on a P-channel MOSFET in high volume manufacturing Reza Arghavani, Li-Qun Xia, Hichem M’Saad, IEEE Electron Device Letters Electrical EngineeringEngineeringStress-induced Leakage CurrentBias Temperature InstabilityMechanical Engineering	2006	38

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