R. Chau

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

K. Mistry, R. Chau, Changhwan Choi et al. · 2007 · 829 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 90-nm logic technology featuring strained-silicon

Scott E. Thompson, M Armstrong, C. Auth et al. · IEEE Transactions on Electron Devices · 2004 · 666 citations

Engineering, Electrical Engineering, Materials Science +17

Benchmarking nanotechnology for high-performance and low power logic transistor applications

R. Chau · 2005 · 573 citations

Engineering, Computer Engineering, Electrical Engineering +17

A Logic Nanotechnology Featuring Strained-Silicon

Scott E. Thompson, M Armstrong, C. Auth et al. · IEEE Electron Device Letters · 2004 · 513 citations

Engineering, Electrical Engineering, Materials Science +17

High-<tex>$kappa$</tex>/Metal–Gate Stack and Its MOSFET Characteristics

R. Chau, Suman Datta, M. Doczy et al. · IEEE Electron Device Letters · 2004 · 468 citations

Engineering, Electrical Engineering, Materials Science +17