A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

K. Mistry, R. Chau, Changhwan Choi, +50

Nm Logic TechnologyEngineeringVlsi DesignComputer ArchitectureHigh Volume +16

A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

C. Auth, C. Allen, A. Blattner, +44

Low-power Cmos TechnologyEngineeringVlsi DesignTri-gate TransistorsIntegrated Circuits +17

A 90-nm logic technology featuring strained-silicon

Scott E. Thompson, M Armstrong, C. Auth, +25

IEEE Transactions on Electron Devices

Electrical EngineeringEngineeringNanoelectronicsStress-induced Leakage CurrentApplied Physics +8

A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors

T. Ghani, M Armstrong, C. Auth, +17

Silicon Cmos TransistorsEngineeringHigh VolumeSilicon On InsulatorSemiconductor Device +15

A Logic Nanotechnology Featuring Strained-Silicon

Scott E. Thompson, M Armstrong, C. Auth, +16

IEEE Electron Device Letters

Electrical EngineeringEngineeringFlexible ElectronicsPhysicsNanoelectronics +10

A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 μm/sup 2/ SRAM cell

Scott E. Thompson, N. Anand, M Armstrong, +41

Nm Logic TechnologyEngineeringVlsi DesignEdge 90Computer Architecture +17

45nm High-k + metal gate strain-enhanced transistors

C. Auth, A. Cappellani, Jang‐Soo Chun, +31

Materials EngineeringElectrical EngineeringEngineeringStress-enhancement TechniquesAdvanced Packaging (Semiconductors) +9

In Search of “Forever,” Continued Transistor Scaling One New Material at a Time

Scott E. Thompson, R. Chau, T. Ghani, +3

IEEE Transactions on Semiconductor Manufacturing

Materials EngineeringElectrical EngineeringNew MaterialEngineeringVlsi Design +13

Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs

A. Keshavarzi, Shuo Ma, S. Narendra, +5

Low-power ElectronicsHardware SecurityElectrical EngineeringPhysical Design (Electronics)Engineering +12

The generation and characterization of electron and hole traps created by hole injection during low gate voltage hot-carrier stressing of n-MOS transistors

B.S. Doyle, Marc Bourcerie, C. Bergonzoni, +4

IEEE Transactions on Electron Devices

Semiconductor TechnologyElectrical EngineeringEngineeringCrystalline DefectsN-mos Transistors +10