T. Ghani

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

K. Mistry, R. Chau, Changhwan Choi et al. · 2007 · 829 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

C. Auth, C. Allen, A. Blattner et al. · 2012 · 758 citations

Engineering, Computer Engineering, Electrical Engineering +16

A 90-nm logic technology featuring strained-silicon

Scott E. Thompson, M Armstrong, C. Auth et al. · IEEE Transactions on Electron Devices · 2004 · 666 citations

Engineering, Electrical Engineering, Materials Science +17

A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors

T. Ghani, M Armstrong, C. Auth et al. · 2004 · 561 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 14nm logic technology featuring 2<sup>nd</sup>-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm<sup>2</sup> SRAM cell size

S. Natarajan, M. Agostinelli, Sheikh A. Akbar et al. · 2014 · 532 citations

Engineering, Computer Engineering, Electrical Engineering +16