C. Prasad

BTI reliability of 45 nm high-K + metal-gate process technology

Sangwoo Pae, M. Agostinelli, M. Brazier et al. · 2008 · 131 citations

Engineering, Electrical Engineering, Materials Science +17

Self-heat reliability considerations on Intel's 22nm Tri-Gate technology

C. Prasad, Lei Jiang, D. Singh et al. · 2013 · 84 citations

Engineering, Computer Engineering, Electrical Engineering +17

Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing

W. Hafez, Prashant Agnihotri, M. Asoro et al. · 2023 · 63 citations

Engineering, Electrical Engineering, High-performance Computing +12

Self-heating in advanced CMOS technologies

C. Prasad, S. Ramey, Lei Jiang · 2017 · 62 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 14 nm SoC platform technology featuring 2<sup>nd</sup> generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um<sup>2</sup> SRAM cells, optimized for low power, high performance and high density SoC products

C.-H. Jan, F. Al-Amoody, H.-Y. Chang et al. · 2015 · 48 citations

Engineering, Computer Engineering, Electrical Engineering +16