H.-Y. Chang

A 14 nm SoC platform technology featuring 2<sup>nd</sup> generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um<sup>2</sup> SRAM cells, optimized for low power, high performance and high density SoC products

C.-H. Jan, F. Al-Amoody, H.-Y. Chang et al. · 2015 · 48 citations

Engineering, Computer Engineering, Electrical Engineering +16

Transistor reliability characterization and comparisons for a 14 nm tri-gate technology optimized for System-on-Chip and foundry platforms

C. Prasad, K. W. Park, Manisha Chahal et al. · 2016 · 24 citations

Engineering, Computer Engineering, Electrical Engineering +17

Combining a Novel Charge-Based Capacitance Measurement (CBCM) Technique and Split $C$–$V$ Method to Specifically Characterize the STI Stress Effect Along the Width Direction of MOSFET Devices

Yao-Wen Chang, H.-Y. Chang, Tao‐Cheng Lu et al. · IEEE Electron Device Letters · 2008 · 12 citations

Engineering, Electrical Engineering, Microelectronics +16

An Intel 3 Advanced FinFET Platform Technology for High Performance Computing and SOC Product Applications

W. Hafez, D. Abanulo, Mahmoud H. Abdel‐Kader et al. · 2024 · 11 citations

Engineering, Electrical Engineering, High-performance Computing +17