Sangwoo Pae

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

K. Mistry, R. Chau, Changhwan Choi et al. · 2007 · 825 citations

Nm Logic Technology, Engineering, Vlsi Design +18

High performance 32nm logic technology featuring 2<sup>nd</sup> generation high-k + metal gate transistors

P. Packan, Sheikh A. Akbar, M Armstrong et al. · 2009 · 184 citations

Nm Logic Technology, Electrical Engineering, Engineering +13

A 32nm logic technology featuring 2<sup>nd</sup>-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm<sup>2</sup> SRAM cell size in a 291Mb array

S. Natarajan, M Armstrong, M. Bost et al. · 2008 · 184 citations

Engineering, Vlsi Design, Channel Strain +17

BTI reliability of 45 nm high-K + metal-gate process technology

Sangwoo Pae, M. Agostinelli, M. Brazier et al. · 2008 · 130 citations

Materials Engineering, Nmos Bti, Electrical Engineering +13

Erratic fluctuations of sram cache vmin at the 90nm process technology node

M. Agostinelli, J. Hicks, Jianzhong Xu et al. · 2006 · 116 citations

Hardware Security, Non-volatile Memory, Electrical Engineering +15