P. Packan - Concepedia

Concepedia

Author

P. Packan

Intel (United States)

Also Known As

P. A. Packan, P. Packan, P.A. Packan, Paul A. Packan, Paul Packan

48

Publications

2.7K

Citations

27

H-Index

59

Concepts

All Affiliations

Intel (United States)Stanford University

PP

About

P. Packan is an author at Intel (United States) specializing in engineering, microelectronics, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	26	33	2.7K
2	Electrical Engineering	24	30	2.5K
3	Computer Engineering	18	19	1.7K
4	Applied Physics	13	15	1.5K
5	Chemical Engineering	1	1	43

P. Packan

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34

Publications

2.7K

Citations

27

H-Index

	Year	Citations
A 14nm logic technology featuring 2<sup>nd</sup>-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 &#x00B5;m<sup>2</sup> SRAM cell size S. Natarajan, M. Agostinelli, Sheikh A. Akbar, -Generation FinfetRectangular FinsEngineeringVlsi DesignIntegrated Circuits	2014	521
Pushing the Limits P. Packan Science EngineeringSocial ChangeTransistor PerformanceSocietal ChallengeTransistor Dimensions	1999	383
High performance 32nm logic technology featuring 2<sup>nd</sup> generation high-k + metal gate transistors P. Packan, Sheikh A. Akbar, M Armstrong, Nm Logic TechnologyElectrical EngineeringEngineeringVlsi DesignNanoelectronics	2009	184
A 32nm logic technology featuring 2<sup>nd</sup>-generation high-k + metal-gate transistors, enhanced channel strain and 0.171&#x03BC;m<sup>2</sup> SRAM cell size in a 291Mb array S. Natarajan, M Armstrong, M. Bost, EngineeringVlsi DesignChannel StrainIntegrated CircuitsSemiconductor Device	2008	184
Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors T. Ghani, K. Mistry, P. Packan, Electrical EngineeringPhysical Design (Electronics)EngineeringVlsi DesignTechnology Scaling	2002	165
A high performance 180 nm generation logic technology Shih‐Chi Yang, Sally Ahmed, B. Arcot, Low-power ElectronicsMaterials EngineeringElectrical EngineeringEngineeringVlsi Design	2002	89
Transient diffusion of low-concentration B in Si due to 29Si implantation damage P. Packan, J.D. Plummer Applied Physics Letters Materials EngineeringMaterials ScienceLow-concentration BB DiffusionEngineering	1990	84
Self-heat reliability considerations on Intel's 22nm Tri-Gate technology C. Prasad, Lei Jiang, D. Singh, EngineeringSelf-heat Reliability ConsiderationsComputer ArchitectureExcellent MatchingThermal Modeling	2013	84
A comparison of state-of-the-art NMOS and SiGe HBT devices for analog/mixed-signal/RF circuit applications Kelin J. Kuhn, R. Basco, D. Becher, Electrical EngineeringEngineeringAnalog/mixed-signal/rf Circuit ApplicationsRf SemiconductorHigh-frequency Device	2004	67
Transistor aging and reliability in 14nm tri-gate technology S. Novak, C. Parker, D. Becher, ReliabilityElectrical EngineeringGate Oxide ReliabilityEngineeringTransistor Optimizations	2015	65

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