J. Hicks

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

K. Mistry, R. Chau, Changhwan Choi et al. · 2007 · 829 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

C. Auth, C. Allen, A. Blattner et al. · 2012 · 758 citations

Engineering, Computer Engineering, Electrical Engineering +16

Intrinsic transistor reliability improvements from 22nm tri-gate technology

S. Ramey, A. Ashutosh, C. Auth et al. · 2013 · 167 citations

Engineering, Electrical Engineering, Electronic Materials +15

BTI reliability of 45 nm high-K + metal-gate process technology

Sangwoo Pae, M. Agostinelli, M. Brazier et al. · 2008 · 131 citations

Engineering, Electrical Engineering, Materials Science +17

Soft Error Rate Improvements in 14-nm Technology Featuring Second-Generation 3D Tri-Gate Transistors

N. Seifert, Shah M. Jahinuzzaman, Jyothi Velamala et al. · IEEE Transactions on Nuclear Science · 2015 · 126 citations

Engineering, Computer Engineering, Electrical Engineering +17