Soft Error Rate Improvements in 14-nm Technology Featuring Second-Generation 3D Tri-Gate Transistors

Abstract

We report on radiation-induced soft error rate (SER) improvements in the 14-nm second generation high- k + metal gate bulk tri-gate technology. Upset rates of memory cells, sequential elements, and combinational logic were investigated for terrestrial radiation environments, including thermal and high-energy neutrons, high-energy protons, and alpha-particles. SER improvements up to ~ 23× with respect to devices manufactured in a 32-nm planar technology are observed. The improvements are particularly pronounced in logic devices, where aggressive fin depopulation combined with scaling of relevant fin parameters results in a ~ 8× reduction of upset rates relative to the first-generation tri-gate technology.