Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Devices

N. Seifert, P. Slankard, Martin Kirsch, +7

Hardware SecurityElectrical EngineeringEngineeringVlsi DesignComprehensive Summary +9

Soft Error Susceptibilities of 22 nm Tri-Gate Devices

N. Seifert, B. Gill, Shah M. Jahinuzzaman, +5

IEEE Transactions on Nuclear Science

EngineeringVlsi DesignNm Planar DevicesComputer ArchitectureSoft Error Susceptibilities +14

Combinational Logic Soft Error Correction

Subhasish Mitra, Ming Zhang, Saad Waqas, +3

Logic SynthesisFuzzy LogicEngineeringError Control TechniqueAutomated Reasoning +9

Soft Error Rate Improvements in 14-nm Technology Featuring Second-Generation 3D Tri-Gate Transistors

N. Seifert, Shah M. Jahinuzzaman, Jyothi Velamala, +5

IEEE Transactions on Nuclear Science

EngineeringVlsi DesignNuclear PhysicsTri-gate TransistorsIntegrated Circuits +14

On the radiation-induced soft error performance of hardened sequential elements in advanced bulk CMOS technologies

N. Seifert, V. Ambrose, B. Gill, +8

EngineeringVlsi DesignComputer ArchitectureDefect ToleranceHardware Security +15

Comparison of alpha-particle and neutron-induced combinational and sequential logic error rates at the 32nm technology node

B. Gill, N. Seifert, V. Zia

IEEE International Reliability Physics Symposium proceedings

Technology NodeEngineeringVlsi DesignComputer ArchitectureUpset Rates +18

Multi-cell upset probabilities of 45nm high-k + metal gate SRAM devices in terrestrial and space environments

N. Seifert, B. Gill, K. Foley, +1

Electrical EngineeringMulti-cell Upset ProbabilitiesEngineeringHardware ReliabilityPhysics +12

An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories

B. Gill, M. Nicolaidis, Francis Wolff, +2

Design, Automation, and Test in Europe

Bics Reliability AnalysisVlsi DesignEngineeringComputer ArchitectureEfficient Bics Design +15

On the Scalability of Redundancy based SER Mitigation Schemes

N. Seifert, B. Gill, V. Zia, +2

EngineeringVlsi DesignSurvivable SystemUpset RateComputer Architecture +17

Node sensitivity analysis for soft errors in CMOS logic

B. Gill, C. Papachristou, Francis Wolff, +1

EngineeringVlsi DesignComputer ArchitectureFormal VerificationHardware Security +15