IEEE Transactions on Nuclear Science · 2012 · 184 citations · 15 references
EngineeringComputer EngineeringElectrical EngineeringFault-tolerant ComputingMicroelectronicsSemiconductor DevicesCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyDevice CharacterizationDevice ReliabilityDevice ScalingHardware Fault ToleranceCombinational Logic DesignLogic DevicesRadiation Effects On ReliabilityRadiation-induced Error MitigationRadiation-tolerant ElectronicsRadiation-tolerant Semiconductor DevicesSoft Error MitigationSoft Error Reliability
The authors introduce a novel, efficient SER reduction design named RTS. They measured radiation‑induced soft‑error rates of memory and logic devices fabricated in 22 nm high‑k metal‑gate bulk Tri‑Gate technology and presented the RTS design for SER reduction. The measurements reveal significant SEU SER reductions compared to 32 nm planar devices for both cosmic radiation and alpha particles, with similar improvements for combinational logic and multi‑cell upset rates, and RSER devices performing on par or better than the planar counterparts.
We report on measured radiation-induced soft error rates (SER) of memory and logic devices built in a 22 nm high-k metal gate bulk Tri-Gate technology. Our results demonstrate excellent single event upset (SEU) scaling benefits of tri-gate devices. For cosmic radiation, SEU SER reduction levels of the order of are observed relative to 32 nm planar devices, while for alpha-particles, the measured SEU SER benefit is in excess of . Similar improvements are observed for Tri-Gate combinational logic and memory array multi-cell upset (MCU) rates. Reduced SER (RSER) device SER performances (relative to standard, non -RSER devices) are on par or better than that of tested 32 nm planar devices. Finally, a novel, efficient SER reduction design called RTS is introduced.
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Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout
Barry M. Doyle, B. I. Boyanov, Suman Datta et al. · 2004 · 219 citations