Concepedia

M. Asoro

MA

Statistics

Publications

3

Citations

445

H-Index

3

Active since

2017

Affiliations

Intel (United States)(Current)

M. Asoro is an author at Intel (United States) specializing in computer engineering, electrical engineering, and microelectronics.

Top concepts

Publications per year

2017–2023

3

Publications

3

A 10nm high performance and low-power CMOS technology featuring 3<sup>rd</sup> generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects

C. Auth, A. Aliyarukunju, M. Asoro et al. · 2017 · 353 citations

, , +18

Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing

W. Hafez, Prashant Agnihotri, M. Asoro et al. · 2023 · 58 citations

, , +16

Interconnect Stack using Self-Aligned Quad and Double Patterning for 10nm High Volume Manufacturing

A. Yeoh, Advait Madhavan, Nicholas Kybert et al. · 2018 · 34 citations

, , +20

Rows per page

1–3 of 3