Concepedia

M. Asoro

MA

Statistics

Publications

4

Citations

479

H-Index

4

Active since

2017

Affiliations

Intel (United States)(Current)

M. Asoro is an author at Intel (United States) specializing in semiconductor devices, engineering, and integrated circuit design.

Publications per year

2017–2025

4

Publications

4

A 10nm high performance and low-power CMOS technology featuring 3<sup>rd</sup> generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects

C. Auth, A. Aliyarukunju, M. Asoro et al. · 2017 · 369 citations

Engineering, Computer Engineering, Electrical Engineering +17

Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing

W. Hafez, Prashant Agnihotri, M. Asoro et al. · 2023 · 63 citations

Engineering, Electrical Engineering, High-performance Computing +12

Interconnect Stack using Self-Aligned Quad and Double Patterning for 10nm High Volume Manufacturing

A. Yeoh, Advait Madhavan, Nicholas Kybert et al. · 2018 · 34 citations

Engineering, Electrical Engineering, Manufacturing Engineering +17

Intel 18A Platform Technology Featuring RibbonFET (GAA) and PowerVia for Advanced High-Performance Computing

K. Fischer, Frank E. Abboud, R. Aggarwal et al. · 2025 · 13 citations

Engineering, Computer Engineering, High-performance Computing +17

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