A. Yeoh

A 10nm high performance and low-power CMOS technology featuring 3^rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects

C. Auth, A. Aliyarukunju, M. Asoro et al. · 2017 · 353 citations

Engineering, Integrated Circuits, High Performance +18

A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm/sub 2/ SRAM cell

Peng Bai, C. Auth, S. Balakrishnan et al. · 2005 · 230 citations

Electrical Engineering, Physical Design (Electronics), Engineering +15

A 32nm logic technology featuring 2<sup>nd</sup>-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm<sup>2</sup> SRAM cell size in a 291Mb array

S. Natarajan, M Armstrong, M. Bost et al. · 2008 · 184 citations

Engineering, Vlsi Design, Channel Strain +17

Copper Die Bumps (First Level Interconnect) and Low-K Dielectrics in 65nm High Volume Manufacturing

A. Yeoh, Ming Chang, C. Pelto et al. · 2006 · 61 citations

Engineering, High Volume, Copper Die Bumps +18

Reliability of dual-damascene local interconnects featuring cobalt on 10 nm logic technology

Flavio Griggio, J. Palmer, Fuxiang Pan et al. · 2018 · 59 citations

Nm Logic Technology, Engineering, New Metallization Scheme +18