K. Fischer

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

K. Mistry, R. Chau, Changhwan Choi et al. · 2007 · 829 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 14nm logic technology featuring 2<sup>nd</sup>-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm<sup>2</sup> SRAM cell size

S. Natarajan, M. Agostinelli, Sheikh A. Akbar et al. · 2014 · 532 citations

Engineering, Computer Engineering, Electrical Engineering +16

MRAM as Embedded Non-Volatile Memory Solution for 22FFL FinFET Technology

O. Golonzka, Juan G. Alzate, Ümüt Arslan et al. · 2018 · 156 citations

Engineering, Computer Engineering, Electrical Engineering +14

2 MB Array-Level Demonstration of STT-MRAM Process and Performance Towards L4 Cache Applications

Juan G. Alzate, Ümüt Arslan, Justin Brockman et al. · 2019 · 102 citations

Engineering, Computer Engineering, Computer Science +10

Dynamics of power MOSFET switching under unclamped inductive loading conditions

K. Fischer, K. Shenai · IEEE Transactions on Electron Devices · 1996 · 100 citations

Engineering, Electrical Engineering, Microelectronics +16