A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications

C.-H. Jan, Uma Bhattacharya, R. Brain, +20

EngineeringVlsi DesignComputer ArchitecturePower ElectronicsHardware Security +16

A 32nm SoC platform technology with 2<sup>nd</sup> generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications

C.-H. Jan, M. Agostinelli, Markus J. Buehler, +41

EngineeringVlsi DesignComputer ArchitectureIntegrated CircuitsHigh Performance +18

An advanced low power, high performance, strained channel 65nm technology

S. Tyagi, C. Kenyon, S.-H. Lee, +18

Low-power ElectronicsElectrical EngineeringEnhanced Transistor PerformanceEngineeringVlsi Design +4

A 65nm CMOS SOC Technology Featuring Strained Silicon Transistors for RF Applications

I. Post, M.S. Akbar, G. Curello, +13

Low-power ElectronicsPmos TransistorsElectrical EngineeringRf ApplicationsEngineering +9

A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors

C.-H. Jan, Peng Bai, S. Biswas, +35

Robust ReliabilityEngineeringVlsi DesignIntegrated CircuitsPower Electronics +15

A 65nm ultra low power logic platform technology using uni-axial strained silicon transistors

C.-H. Jan, Peng Bai, Jaeseok Choi, +29

Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignEdge 65Nm +7

A 32nm low power RF CMOS SOC technology featuring high-k/metal gate

P. Vandervoorn, M. Agostinelli, S.-J. Choi, +31

Low-power ElectronicsElectrical EngineeringEngineeringHigh-k/metal GateRf Semiconductor +11

Electrical, optical and materials properties of ion beam synthesised (IBS) FeSi2

K.J. Reeson, M.S. Finney, M. Harry, +9

Nuclear Instruments and Methods in Physics Research Section B Beam Interactions with Materials and Atoms

Materials EngineeringMaterials ScienceElectrical EngineeringOptical MaterialsEngineering +7

Reliability studies of a 22nm SoC platform technology featuring 3-D tri-gate, optimized for ultra low power, high performance and high density application

Anisur Rahman, Peng Bai, G. Curello, +9

Reliability3D Ic ArchitectureElectrical EngineeringReliability EngineeringEngineering +13

Reliability studies of a 32nm System-on-Chip (SoC) platform technology with 2<inf>nd</inf> generation high-k/metal gate transistors

Anisur Rahman, M. Agostinelli, Peng Bai, +10

ReliabilitySystem On ChipElectrical EngineeringReliability EngineeringEngineering +11