R. Brain

A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications

C.-H. Jan, Uma Bhattacharya, R. Brain et al. · 2012 · 303 citations

Engineering, Vlsi Design, Computer Architecture +18

A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm/sub 2/ SRAM cell

Peng Bai, C. Auth, S. Balakrishnan et al. · 2005 · 230 citations

Electrical Engineering, Physical Design (Electronics), Engineering +15

A 32nm logic technology featuring 2<sup>nd</sup>-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm<sup>2</sup> SRAM cell size in a 291Mb array

S. Natarajan, M Armstrong, M. Bost et al. · 2008 · 184 citations

Engineering, Vlsi Design, Channel Strain +17

Low-k interconnect stack with a novel self-aligned via patterning process for 32nm high volume manufacturing

R. Brain, S. Agrawal, D. Becher et al. · 2009 · 34 citations

Engineering, Computer Architecture, Interconnect (Integrated Circuits) +19

A 22nm high performance embedded DRAM SoC technology featuring tri-gate transistors and MIMCAP COB

R. Brain, A. Baran, Nabhendra Bisnik et al. · 2013 · 17 citations

Non-volatile Memory, Engineering, Mimcap Cob +19