2005 · 65 citations · 0 references
EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyIntegrated Circuit DesignShort-channel EffectsStrain EngineeringCurrentsDevice OptimizationHigh PerformanceLeakage Current ReductionLow-power Cmos DesignUltra-low-power Cmos
An advanced low power, strained channel, dual poly CMOS 65nm technology with enhanced transistor performance is presented. At 1V and off current of 100nA/mum, transistors have record currents of 1.21mA/mum and 0.71mA/mum for NMOS and PMOS respectively. This industry leading 65nm technology is currently in high volume manufacturing