Miao Liu

A 14nm logic technology featuring 2<sup>nd</sup>-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm<sup>2</sup> SRAM cell size

S. Natarajan, M. Agostinelli, Sheikh A. Akbar et al. · 2014 · 532 citations

Engineering, Computer Engineering, Electrical Engineering +16

A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm/sub 2/ SRAM cell

C. Auth, S. Balakrishnan, M. Bost et al. · 2005 · 230 citations

Engineering, Computer Engineering, Electrical Engineering +17

High performance 32nm logic technology featuring 2<sup>nd</sup> generation high-k + metal gate transistors

P. Packan, Sheikh A. Akbar, M Armstrong et al. · 2009 · 187 citations

Engineering, Computer Engineering, Electrical Engineering +12

Transistor aging and reliability in 14nm tri-gate technology

S. Novak, C. Parker, D. Becher et al. · 2015 · 65 citations

Engineering, Electrical Engineering, Electronic Materials +16

An advanced low power, high performance, strained channel 65nm technology

S. Tyagi, C. Kenyon, S.-H. Lee et al. · 2005 · 65 citations

Engineering, Electrical Engineering, Microelectronics +13