Concepedia

Transistor aging and reliability in 14nm tri-gate technology

S. Novak, C. Parker, D. Becher, Miao Liu, M. Agostinelli, Manisha Chahal, P. Packan, P. Nayak, S. Ramey, S. Natarajan

2015 · 65 citations · 10 references

Concepts

EngineeringElectrical EngineeringElectronic MaterialsMicroelectronicsSemiconductor DevicesDevice CharacterizationDevice ModelingDevice ReliabilityDevice ScalingReliability ModelingSemiconductor ReliabilityDevice Scaling EffectsGate Oxide DegradationGate Oxide ReliabilityGate Oxide ScalingHigh-k DielectricsMetal Gate ElectrodesReliability MetricsTransistor Scaling

Abstract

This paper details the transistor aging and gate oxide reliability of Intel's 14nm process technology. This technology introduces Intel's 2 nd generation tri-gate transistor and the 4 th generation of high-κ dielectrics and metal-gate electrodes. The reliability metrics reported here highlight reliability gains attained through transistor optimizations as well as intrinsic challenges from device scaling.

References

10

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Engineering, Computer Engineering, Electrical Engineering +16

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Engineering, Computer Engineering, Electrical Engineering +17

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Engineering, Computer Engineering, Electrical Engineering +16

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Engineering, Electrical Engineering, Microelectronics +16

Intrinsic transistor reliability improvements from 22nm tri-gate technology

S. Ramey, A. Ashutosh, C. Auth et al. · 2013 · 167 citations

Engineering, Electrical Engineering, Electronic Materials +15