C. Parker - Concepedia

Concepedia

Author

C. Parker

Intel (United States)ORCID

Also Known As

C. Parker, Christopher B. Parker, Christopher Bennett Parker

17

Publications

1.6K

Citations

8

H-Index

18

Concepts

All Affiliations

Intel (United States)

CP

About

C. Parker is an author at Intel (United States) specializing in electrical engineering, microelectronics, and nanoelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	8	8	1.6K
2	Electrical Engineering	8	8	1.6K
3	Computer Engineering	6	6	1.4K
4	Applied Physics	4	4	1.1K
5	Computer Architecture	1	1	230

C. Parker

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8

Publications

1.6K

Citations

8

H-Index

	Year	Citations
A 14nm logic technology featuring 2<sup>nd</sup>-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 &#x00B5;m<sup>2</sup> SRAM cell size S. Natarajan, M. Agostinelli, Sheikh A. Akbar, -Generation FinfetRectangular FinsEngineeringVlsi DesignIntegrated Circuits	2014	521
A 10nm high performance and low-power CMOS technology featuring 3<sup>rd</sup> generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects C. Auth, A. Aliyarukunju, M. Asoro, EngineeringIntegrated CircuitsHigh PerformanceInterconnect (Integrated Circuits)High-speed Electronics	2017	353
A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm/sub 2/ SRAM cell Peng Bai, C. Auth, S. Balakrishnan, Electrical EngineeringPhysical Design (Electronics)EngineeringVlsi DesignChannel Strain	2005	230
High performance 32nm logic technology featuring 2<sup>nd</sup> generation high-k + metal gate transistors P. Packan, Sheikh A. Akbar, M Armstrong, Nm Logic TechnologyElectrical EngineeringEngineeringVlsi DesignNanoelectronics	2009	184
A 32nm logic technology featuring 2<sup>nd</sup>-generation high-k + metal-gate transistors, enhanced channel strain and 0.171&#x03BC;m<sup>2</sup> SRAM cell size in a 291Mb array S. Natarajan, M Armstrong, M. Bost, EngineeringVlsi DesignChannel StrainIntegrated CircuitsSemiconductor Device	2008	184
Transistor aging and reliability in 14nm tri-gate technology S. Novak, C. Parker, D. Becher, ReliabilityElectrical EngineeringGate Oxide ReliabilityEngineeringTransistor Optimizations	2015	65
Performance and Variability Comparisons between Multi-Gate FETs and Planar SOI Transistors A. V-Y. Thean, Z-H Shi, L. Mathew, Device ModelingElectrical EngineeringUndoped Channel DevicesEngineeringPlanar Soi Transistors	2006	33
Gate dielectric TDDB characterizations of advanced High-k and metal-gate CMOS logic transistor technology Sangwoo Pae, C. Prasad, S. Ramey, Electrical EngineeringEngineeringVlsi DesignNanoelectronicsBias Temperature Instability	2012	18

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