S. Tyagi

A 90-nm logic technology featuring strained-silicon

Scott E. Thompson, M Armstrong, C. Auth et al. · IEEE Transactions on Electron Devices · 2004 · 654 citations

Electrical Engineering, Engineering, Nanoelectronics +10

A Logic Nanotechnology Featuring Strained-Silicon

Scott E. Thompson, M Armstrong, C. Auth et al. · IEEE Electron Device Letters · 2004 · 511 citations

Electrical Engineering, Engineering, Flexible Electronics +12

A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm/sub 2/ SRAM cell

Peng Bai, C. Auth, S. Balakrishnan et al. · 2005 · 230 citations

Electrical Engineering, Physical Design (Electronics), Engineering +15

In Search of “Forever,” Continued Transistor Scaling One New Material at a Time

Scott E. Thompson, R. Chau, T. Ghani et al. · IEEE Transactions on Semiconductor Manufacturing · 2005 · 191 citations

Materials Engineering, Electrical Engineering, New Material +15

Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors

T. Ghani, K. Mistry, P. Packan et al. · 2002 · 165 citations

Electrical Engineering, Physical Design (Electronics), Engineering +11