A 90-nm logic technology featuring strained-silicon

Scott E. Thompson, M Armstrong, C. Auth, +25

IEEE Transactions on Electron Devices

Electrical EngineeringEngineeringNanoelectronicsStress-induced Leakage CurrentApplied Physics +8

A Logic Nanotechnology Featuring Strained-Silicon

Scott E. Thompson, M Armstrong, C. Auth, +16

IEEE Electron Device Letters

Electrical EngineeringEngineeringFlexible ElectronicsPhysicsNanoelectronics +10

A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm/sub 2/ SRAM cell

Peng Bai, C. Auth, S. Balakrishnan, +32

Electrical EngineeringPhysical Design (Electronics)EngineeringVlsi DesignChannel Strain +13

In Search of “Forever,” Continued Transistor Scaling One New Material at a Time

Scott E. Thompson, R. Chau, T. Ghani, +3

IEEE Transactions on Semiconductor Manufacturing

Materials EngineeringElectrical EngineeringNew MaterialEngineeringVlsi Design +13

Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors

T. Ghani, K. Mistry, P. Packan, +4

Electrical EngineeringPhysical Design (Electronics)EngineeringVlsi DesignTechnology Scaling +9

A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects

S. Tyagi, Morteza S. Alavi, R. Bigwood, +21

EngineeringVlsi DesignDual Vt TransistorsComputer ArchitectureNm Transistors +14

An advanced low power, high performance, strained channel 65nm technology

S. Tyagi, C. Kenyon, S.-H. Lee, +18

Low-power ElectronicsElectrical EngineeringEnhanced Transistor PerformanceEngineeringVlsi Design +4

An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7 - 1.4 V

Scott E. Thompson, Morteza S. Alavi, Reza Arghavani, +23

Low-power ElectronicsLow PowerElectrical EngineeringNm TechnologyEngineering +13

Surface recombination velocity and lifetime in InP

Shilpa Bothra, S. Tyagi, S. K. Ghandhi, +1

Solid-State Electronics

Surface CharacterizationEngineeringPhysicsSurface AnalysisSurface Science +2

Source/drain extension scaling for 0.1 μm and below channel length MOSFETs

Scott E. Thompson, P. Packan, T. Ghani, +7

Electrical EngineeringEngineeringVlsi DesignSource/drain ExtensionTechnology Scaling +8