J. Sebastián

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

K. Mistry, R. Chau, Changhwan Choi et al. · 2007 · 825 citations

Nm Logic Technology, Engineering, Vlsi Design +18

Different Purpose Design Strategies and Techniques to Improve the Performance of a Dual Active Bridge With Phase-Shift Control

Alberto Rodríguez, Aitor Vázquez, Diego G. Lamar et al. · IEEE Transactions on Power Electronics · 2014 · 333 citations · Full text

Electrical Engineering, Bridge Design, Engineering +12

An overall study of a Dual Active Bridge for bidirectional DC/DC conversion

Alberto Rodríguez, J. Sebastián, Diego G. Lamar et al. · 2010 · 294 citations

Electrical Engineering, Dual Active Bridge, Engineering +10

A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm/sub 2/ SRAM cell

Peng Bai, C. Auth, S. Balakrishnan et al. · 2005 · 230 citations

Electrical Engineering, Physical Design (Electronics), Engineering +15

An Insight into the Switching Process of Power MOSFETs: An Improved Analytical Losses Model

Miguel A. Rodrı́guez, Alberto Rodríguez, Pablo F. Miaja et al. · IEEE Transactions on Power Electronics · 2010 · 195 citations · Full text

Engineering, Energy Efficiency, Power Electronics Converter +16