J. Sebastián - Concepedia

Author

J. Sebastián

Also Known As

J. SEBASTIÁN, J. Sebastian, J. Sebastián, Javier Sebastian, Javier SebastiÁn ZÚÑiga, Javier Sebastián, Javier Sebastián Zúniga, Sebastian, John

333

Publications

7.8K

Citations

H-Index

Concepts

All Affiliations

Universidad de Oviedo Universidad Politécnica de Madrid European Space Research and Technology Centre

About

J. Sebastián is an author at Universidad de Oviedo specializing in engineering, electrical engineering, and power electronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	44	131	6.7K
2	Electrical Engineering	43	125	6.6K
3	Computer Engineering	19	27	2.2K
4	Applied Physics	3	3	1K
5	Education	2	2	94

J. Sebastián

142

Publications

7.2K

Citations

H-Index

Page 1

	Year	Citations
A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging K. Mistry, R. Chau, Changhwan Choi, Nm Logic TechnologyEngineeringVlsi DesignComputer ArchitectureHigh Volume	2007	825
Different Purpose Design Strategies and Techniques to Improve the Performance of a Dual Active Bridge With Phase-Shift Control Alberto Rodríguez, Aitor Vázquez, Diego G. Lamar, IEEE Transactions on Power Electronics Electrical EngineeringBridge DesignEngineeringDual Active BridgeZvs Operation	2014	333
An overall study of a Dual Active Bridge for bidirectional DC/DC conversion Alberto Rodríguez, J. Sebastián, Diego G. Lamar, Electrical EngineeringDual Active BridgeEngineeringOverall StudyEnergy Management	2010	294
A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm/sub 2/ SRAM cell Peng Bai, C. Auth, S. Balakrishnan, Electrical EngineeringPhysical Design (Electronics)EngineeringVlsi DesignChannel Strain	2005	230
An Insight into the Switching Process of Power MOSFETs: An Improved Analytical Losses Model Miguel A. Rodrı́guez, Alberto Rodríguez, Pablo F. Miaja, IEEE Transactions on Power Electronics EngineeringEnergy EfficiencyPower Electronics ConverterElectric Power ConversionPower Electronic Systems	2010	195
High performance 32nm logic technology featuring 2<sup>nd</sup> generation high-k + metal gate transistors P. Packan, Sheikh A. Akbar, M Armstrong, Nm Logic TechnologyElectrical EngineeringEngineeringVlsi DesignNanoelectronics	2009	184
A 32nm logic technology featuring 2<sup>nd</sup>-generation high-k + metal-gate transistors, enhanced channel strain and 0.171&#x03BC;m<sup>2</sup> SRAM cell size in a 291Mb array S. Natarajan, M Armstrong, M. Bost, EngineeringVlsi DesignChannel StrainIntegrated CircuitsSemiconductor Device	2008	184
Design criteria for SEPIC and Cuk converters as power factor preregulators in discontinuous conduction mode Domingos Sávio Lyrio Simonetti, J. Sebastián, Fernando S. dos Reis, Fly-back TopologiesElectrical EngineeringCuk ConvertersEngineeringDiscontinuous Conduction Mode	2003	161
Design of a Soft-Switching Asymmetrical Half-Bridge Converter as Second Stage of an LED Driver for Street Lighting Application Manuel Arias, Diego G. Lamar, F.F. Linera, IEEE Transactions on Power Electronics Electrical EngineeringSecond StageStreet Lighting ApplicationEngineeringHigh-brightness Leds	2011	157
The determination of the boundaries between continuous and discontinuous conduction modes in PWM DC-to-DC converters used as power factor preregulators J. Sebastián, J.A. Cobos, J.M. Lopera, IEEE Transactions on Power Electronics Electrical EngineeringDiscontinuous Conduction ModesEngineeringConduction ModePwm Dc-to-dc	1995	140

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