H. Deshpande

High performance 32nm logic technology featuring 2<sup>nd</sup> generation high-k + metal gate transistors

P. Packan, Sheikh A. Akbar, M Armstrong et al. · 2009 · 184 citations

Nm Logic Technology, Electrical Engineering, Engineering +13

A 32nm logic technology featuring 2<sup>nd</sup>-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm<sup>2</sup> SRAM cell size in a 291Mb array

S. Natarajan, M Armstrong, M. Bost et al. · 2008 · 184 citations

Engineering, Vlsi Design, Channel Strain +17

RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications

C.-H. Jan, M. Agostinelli, H. Deshpande et al. · 2010 · 84 citations

Engineering, Vlsi Design, Rf Soc +16

A 32nm SoC platform technology with 2<sup>nd</sup> generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications

C.-H. Jan, M. Agostinelli, Markus J. Buehler et al. · 2009 · 75 citations

Engineering, Vlsi Design, Computer Architecture +20

An advanced low power, high performance, strained channel 65nm technology

S. Tyagi, C. Kenyon, S.-H. Lee et al. · 2005 · 63 citations

Low-power Electronics, Electrical Engineering, Enhanced Transistor Performance +6