Low-k interconnect stack with multi-layer air gap and tri-metal-insulator-metal capacitors for 14nm high volume manufacturing

Abstract

We describe here Intel's 14nm high-performance logic technology interconnects and back end stack featuring 13 metal layers and a tri-metal laminated metal-insulator-metal (MIM) capacitor. For the first time on a logic product in high volume, multiple layers (M4 and M6) incorporate an air gap integration scheme to deliver up to 17% RC benefit. Pitch Division patterning is introduced to deliver high yield capable interconnect layers with a minimum pitch of 52nm.