M. Haran

A 14nm logic technology featuring 2<sup>nd</sup>-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm<sup>2</sup> SRAM cell size

S. Natarajan, M. Agostinelli, Sheikh A. Akbar et al. · 2014 · 521 citations

-Generation Finfet, Rectangular Fins, Engineering +16

A 10nm high performance and low-power CMOS technology featuring 3^rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects

C. Auth, A. Aliyarukunju, M. Asoro et al. · 2017 · 353 citations

Engineering, Integrated Circuits, High Performance +18

Low-k interconnect stack with multi-layer air gap and tri-metal-insulator-metal capacitors for 14nm high volume manufacturing

K. Fischer, M. Agostinelli, C. Allen et al. · 2015 · 67 citations

Engineering, Vlsi Design, Logic Product +19

Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing

W. Hafez, Prashant Agnihotri, M. Asoro et al. · 2023 · 58 citations

Engineering, Vlsi Design, Energy Efficiency +16

Intel 4 CMOS Technology Featuring Advanced FinFET Transistors optimized for High Density and High-Performance Computing

B. Sell, Seungchan An, Jeffrey L. Armstrong et al. · 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 2022 · 40 citations