Enabling Next Generation 3D Heterogeneous Integration Architectures on Intel Process

Abstract

This paper discusses a new generation of heterogeneous integration architectures which we refer to as quasi-monolithic chips (QMC). QMC enables flexible out-of-order combinations of silicon process & packaging techniques to create flexible and ultra-high interconnect density 3D architectures to fit future computing & AI needs. We show the main structural elements of the architecture and its performance including up to 10X interconnect power reduction and density improvements. We also cover the main new process modules needed to enable QMC including high density back-end compatible hybrid bonding and ultra-thick oxide fill modules.