Concepedia

Characterization and Optimization of Sub-32-nm FinFET Devices for ESD Applications

S. Thijs, David Trémouilles, Christian Russ, Alessio Griffoni, Nadine Collaert, R. Rooyackers, Dimitri Linten, Mirko Scholz, Charvaka Duvvury, M. Jurczak,

IEEE Transactions on Electron Devices · 2008 · 17 citations · 12 references

DOI

Concepts

Abstract

Electrostatic discharge performance of advanced FinFETs shows a delicate sensitivity to device layout and to processing parameters. Both N- and P-type MOS FinFET devices are characterized in bipolar operation mode as a function of layout parameters such as gate length and fin width. The impact of well implants, selective epitaxial growth, and strain is studied.

References

12

Analysis of the Parasitic S/D Resistance in Multiple-Gate FETs

Abhisek Dixit, Anil Kottantharayil, Nadine Collaert et al. · IEEE Transactions on Electron Devices · 2005 · 355 citations

, , +16

Extension and source/drain design for high-performance finFET devices

J. Kedzierski, M. Ieong, E. Nowak et al. · IEEE Transactions on Electron Devices · 2003 · 244 citations

, , +16

Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO<sub>2</sub> gate dielectrics

Min Yang, E. P. Gusev, M. Ieong et al. · IEEE Electron Device Letters · 2003 · 166 citations

, , +17

Multi-gate devices for the 32nm technology node and beyond

Nadine Collaert, A. De Keersgieter, Abhisek Dixit et al. · 2007 · 60 citations

, , +16

Performance improvement of tall triple gate devices with strained SiN layers

Nadine Collaert, A. De Keersgieter, K.G. Anil et al. · IEEE Electron Device Letters · 2005 · 49 citations

, , +17